Careers
Life at Sequentia
Organizational culture
Sequentia’s organizational structure is designed to be flexible and innovative that cultivates creativity and productivity.
At Sequentia we come together with a “Will DO” spirit. Our teams are the driving force propelling us to scale new heights. Well-rounded individuals, thorough professionals, knowledge Gurus – Sequentians fit this description. Working on the most aggressive process technologies and a variety of projects across domains, our engineers are always up for a challenge and to cross new frontiers.
New ideas are encouraged and achieved from every level of the organization. The diversity of team members from around the world work together to achieve customers’ success and satisfaction, the true measure of success
An open work culture with an interactive atmosphere encourages collaboration across teams and breeds innovation. Supporting each other and teaming up to explore beyond what is known. Ever growing skill sets and information enriches the inquisitive minds.
Opportunities galore, paving the way for successful careers. Performance and the right spirit rewarded amply. Sequentia grows as their teams scale higher.
FOOD
We endeavor to provide our employees with benefits, especially in terms of providing them with subsidized food
Exciting work and challenge
Being a complete technological organization, we offer our employees with exciting opportunities to work on latest technologies. We firmly uphold the belief that a healthy dose of fun elements also needs to be incorporated in the day-to-day work, in order to maintain a balance.
This is the opposite of boredom. Boredom leads to a loss in productivity and focus. Rather than letting our employees just go through the motions, we challenge them with stimulating work that has a direct impact on our company’s success.
Career growth, learning, and development
Sequentia aim to foster a desire among employees to want to stay with our company. One of the key elements in an “employee’s intention to leave” is their level of commitment to the organization. Commitment is directly related to opportunities for employee development, so by offering training we are cultivating commitment.
EMPLOYEE BENEFITS
Over and above an exciting career, growth and a great experience, Sequentia also ensures its members are well taken care of. Sequentia offers excellent benefits comparable to those offered in the industry
Paid Time Off
There is flexibility for our workforce in times of need. The leaves cover from Maternity-Paternity Leaves and Holidays
Sequentia Offer a competitive benefits package that fits our employees’ needs, we also, provide meaningful annual raises. Apart from compensation other perks, such as flexible time and the option of telecommuting to accommodate their outside lives.
Assistance
Employee Assistance Program which helps maintain healthy psychology and overall wellbeing
Verification 2-7 years Exp
• Developing test plans
• UVM and C++ coding for test bench components
• Maintaining existing UVM / C++ test bench components
• Debugging fails
• Functional coverage , code coverage planning, development and closure
• Protocols experience USB2/USB3 , Ethernet, DDR3/4, PCIe , MIPI, UFS
ASIC Emulation Engineer 2-7 years Exp
• Full chip Emulation with 2 to 7 yrs of exp
• Develop system level tests using python, C/C++ and SV, implement test plans
• Map designs into emulator platforms, mapping FPGA libraries
• Define verification / emulation methodologies
• Debug and resolve Pre / Post Silicon failures
• exp on Zebu or palladium, 2 min projects completed
FPGA Prototyping 2 to 7 yrs of exp
• FPGA Prototyping methodologies, 2 to 7 yrs of exp
• design partitioning SOC designs into multiple FPGAs , mapping FPGA libraries
• constraints generation, , place and route, FPGA RTL simulation, , Validation on HAPS80/70 series, FPGA boards, Board bring-up, System Debug
• Firmware stitching and system validation
ASIC Synthesis 3-10 years
• VHDL or System Verilog. Synthesis, LEC, low power checks, Memory BIST insertion, SDC validation. Development of signoff quality SDC constraints running RTL Lint, CLP, MEMBIST, DFT DRC etc. Hands-on with Synopsys DC Prime Time including Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
Physical Design: 3-10 years
• block / SOC level netlist – gds2 experience.
• Expertise in Floorplaning , Power planning , CTS. Should be capable of handling block – level timing closure. low powersignoff checks , like MVRC / CLP , LEC / Formality , DRC , LVS , IR , EM. Good scripting skills (TCL / SHELL).
Address
Mahadevapura,
Outer Ring Road.
Bangalore